Design of power amplifiers at 2.4 GHz/900 MHz and implementation of on-chip linearization technique in 0.18/0.25/spl mu/m CMOS

This paper presents a step by step design of power amplifiers at 2.4 GHz (for WLAN applications) and on-chip linearization of these amplifiers. CMOS power amplifiers are designed at 2.4 GHz with output power ranging from 30 mW to 100 mW with efficiency varying from 20%-40%. Two or three stages are cascaded according to the gain and efficiency requirements. The topology used for 2.4 GHz amplifier is also verified as a part of an FM transmitter at 900 MHz. All these integrated power amplifiers are not intended to have a very good linearity. At the later part of this work, feedforward technique is used for linearization of a 2.4 GHz two-stage power amplifier in 0.25 /spl mu/m CMOS8 process. The power output of the linear amplifier (in push-pull configuration) is 17 dBm with 20% efficiency. The in-band non-linearity (from two-tone simulations) is given by 3/sup rd/ order inter-modulation product and is about 40 dBc. For on-chip combining, transformers and baluns are used. All the circuits are simulated using CADENCE tools (ICFB). Inductors, transformers and baluns are designed and simulated using ASITIC tools. The power amplifiers are currently under fabrication in CMOS8 (0.25 /spl mu/m) and CMOS9 (0.18 /spl mu/m) processes.