High-performance and low-cost 0.15-/spl mu/m nMOSFETs using simultaneous N-gate and source/drain doping process

A fabrication method for high performance and low cost nMOSFETs suitable for 0.15 and sub-0.15 /spl mu/m CMOS technology is proposed. In this method, n-poly gate doping prior to the definition of gate poly was skipped, i.e., gate poly is simultaneously doped by the source/drain ion implantation. Then, the source/drain implantation dose was increased by the amount used for gate pre-doping process. Although gate pre-doping is skipped, device performances such as device on-off current characteristics, active and poly sheet resistance and junction leakage current are compatible to the pre-doping ones. Moreover, the proposed method has the advantages of low cost and high yield because one mask step and several processes are reduced. The degree of active damage by the doubled source/drain implantation dose was investigated using the transmission electron microscopy, and high resolution x-ray diffraction spectroscopy.