A statistical model for extracting geometric sources of transistor performance variation

This paper provides an approach to extracting geometrical variations in nominally identical devices fabricated in close proximity to each other. The method assumes correlations between factors can be neglected. With this assumption, it is shown that geometrical variations are significant, and any study of microscopic variations, such as dopant fluctuations, must first strip away these macroscopic geometrical variations. We assess the gate length L and width W dependence of threshold voltage (V/sub T/) variations. Related geometrical variations, namely corner influences where the source and drain encounter the isolation edges are examined, and incorporated in the model. Results from the model are compared to measurements at small dimensions. The differences provide lower bounds for excess variations other than these geometrical contributions. Our study shows that these other variations account for almost half the total V/sub T/ variance at the smallest device size fabricated, demonstrating the seriousness of these other variations when scaling down devices.