Charging effects on medium current implanter on CMOS and mixed signal IC's

Stringent process performance requirements for advanced devices have led to hardware specifically optimized for low metal contamination and particle contribution during implants and wafer handling. Electrostatic chucks (ESC) serve this purpose particularly well in single wafer processing machines in that the area of the wafer holder exposed to the beam can be nearly completely eliminated. One potential disadvantage of this is that secondary electrons are no longer generated in the wafer vicinity to neutralize the beam. Wafer charging was observed for certain implant levels for CMOS and mixed signal integrated circuits, implanted on an Axcelis 8200/8250 medium current implanter with the Electrostatic Chuck using no electron shower for beam neutralization. The charging effects were manifested as blowouts/arcing defects on the silicon surface, as verified by in-line defectivity metrology. Depressed yield was also observed for the wafers impacted by the charging problem even in the case with no visible in-line defectivity. The charging intensity and resulting extent of damage was found to vary with beam current. Addition of secondary electron shower module to provide charge control is shown to eliminate the problem. Wafer charging in response to various settings of electron shower primary current is discussed by review of in-line defectivity/silicon damage measurements and end of the line yield data. Equipment and process optimizations to improve system performance and stability are summarized.