Dynamic biasing: a low power linearisation technique

A highly linear opamp processed in a 0.25/spl mu/m 2 V CMOS technology suitable for an intermediate frequency (IF) continuous time sigma-delta analog-to-digital converter (/spl Sigma//spl Delta/ ADC) is presented. Due to an improved technique, called dynamic biasing, distortion components in an IF band, typically situated at frequencies from 1 to 10 MHz for a low-IF receiver architecture, are lowered without any signal degeneration. The circuit achieves an IIP3 and an IIP5 of more than 20 dBm. The power consumption is limited to 3.4 mW.