Scaling of high-k dielectrics towards sub-1nm EOT

High-k dielectric layers are deposited using ALD or MOCVD. Most of the work focused on Hf-based high-k dielectrics, either as pure HfO/sub 2/, as silicate or mixed with Al/sub 2/O/sub 3/. In some cases nitrogen is added to improve the high-temperature stability. Various surface preparation methods and deposition conditions are tested. Compatibility of the high-k stacks with poly-Si and metal electrodes is investigated. Significant improvements in yield and thermal stability are obtained by optimized modifications of the high-k stack. Scaling of the equivalent oxide thickness (EOT) is accomplished by implementing novel ideas in interface engineering and high-k materials processing. High-k stacks are tested in transistor structures with small gate lengths. The origin of the electrical instabilities and the observed drive current degradation of high-k transistors as compared to the SiO/sub 2/ reference transistors are studied in detail.