Metal gate NMOSFETs with TaSiN/TaN stacked electrode fabricated by a replacement (damascene) technique

This letter describes a replacement (damascene) metal gate NMOSFET with TaSiN and PVD TaN as stacked gate electrode. The goal is to perform the "gate electrode engineering" in order to change the work function and the threshold voltage of the transistor. An annealing at 400/spl deg/C after the metal gate is formed significantly improves the transistor performance. The subthreshold slope is measured to be around 65 mV/decade. The oxide/silicon interface states density (Dit) is measured to be 6.4/spl times/10/sup 10/ cm/sup -2/ eV/sup -1/. The low Dit indicates that the plasma damage (from the polysilicon dry etching and the PVD metal deposition) can be minimized by a post-fabrication annealing at a relatively low temperature.