Construction of VHDL-AMS simulator in Matlab

We describe the digital kernel implementation of the simulator S.A.M.S.A., a tool for the simulation of VHDL-AMS systems in Matlab/sup /spl trade//. The digital kernel was validated by simulating different systems. In particular we will show the simulation of a low-power multistage decimator for a wideband /spl Delta/-/spl Sigma/ analog to digital converter (ADC). This example was correctly simulated given the same results as other VHDL commercial tools.