Abstract:
An output buffer circuit with an adjustable output impedance and high linearity is presented. The buffer circuit employs two kinds of feedback strategies, which enable it...Show MoreMetadata
Abstract:
An output buffer circuit with an adjustable output impedance and high linearity is presented. The buffer circuit employs two kinds of feedback strategies, which enable it to drive a low impedance load without power increase. A differential buffer circuit with 20-ohm output impedance has been fabricated in a 0.25-/spl mu/m CMOS process. The measured IIP3 is over 30 dBm for frequencies up to 100 MHz and the power consumption is 93.1 mW with a 3.3-V power supply.
Date of Conference: 24-24 September 2003
Date Added to IEEE Xplore: 03 December 2003
Print ISBN:0-7803-7842-3
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