Statistical leakage current reduction by self-timed cut-off scheme for high leakage environments

This paper describes a statistical leakage current reduction scheme that can reduce leakage current even if the chip is in an active mode. The scheme utilizes a self-timed cut-off switch that puts a given block into a sleep mode if the block is not used for a certain number of cycles. The effectiveness of the proposed scheme is verified by an 8-bit RISC microprocessor using Verilog HDL, and demonstrated by a 64 bit carry look ahead adder fabricated with dual-V/sub TH/ SOI technology.