A 16-bit, 20MSPS CMOS pipeline ADC with direct INL detection algorithm

A 16-bit, 20 MSPS, 5 V pipeline ADC is implemented on a double poly, triple metal 0.5 /spl mu/m CMOS process with a digital calibration algorithm that directly detects INL of MDACs. The measured INL and DNL are +3.5/-2.0 LSBs and /spl plusmn/0.6 LSBs, respectively. For a 5 MHz full scale input at 20 MSPS, it achieves 78 dB SNR and 91dB SFDR, consuming 750 mW. The die size is 6.23 mm/spl times/7.22 mm.