Pipelined match-lines and hierarchical search-lines for low-power content-addressable memories

This paper presents a pipelined match-line and a hierarchical search-line architecture to reduce power in content-addressable memories (CAM). The overall power reduction is 60%, with 29% contributed by the pipelined match-lines and 31% contributed by the hierarchical search-lines. This proposed architecture is employed in the design of a 1024/spl times/144 bit ternary CAM, achieving 7 ns search cycle time at 2.89 fJ/bit/search in a 0.18 /spl mu/m CMOS process.