A substrate noise analysis methodology for large-scale mixed-signal ICs

A substrate noise analysis methodology is described that simulates substrate noise waveforms at sensitive locations of large-scale mixed-signal ICs. Simulation results for a 7.3 mm/spl times/7.3 mm chip with 500 k devices, obtained in a few hours on an engineering server, show good correlation with silicon measurements as testing conditions are varied. An analysis of the substrate and package reveals the importance of modeling inductive coupling between neighboring switching and quiet ground pins due to the substrate return of currents between them.