Transformation-based layout optimization

An approach to layout optimization that involves invoking a set of transformations on an initial symbolic layout is presented. The tools work well together, providing a high degree of user-controllability. The tools run on selected areas or the whole chip, honor the user's modifications, perform with partial layouts and ERC/LVS errors, and have separate and clearly defined optimizations. The tools are fast and practical. Using these transformations, the quality of the layout of six industrial, block-oriented design is greatly improved. On average, the routing area is reduced by 15%, the number of contacts by 38%, and the wire length by 11%.<
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