A VLSI DPCM encoder/decoder chip set for extended quality digital TV

An experimental prototype video DPCM (differential pulse code modulation) chip set has been designed and fabricated with 2- mu m CMOS technology. The die size for the encoder is 8500 mu m*7600 mu m with 48000 transistors. The decoder is a pad-limited design: it measures 5800 mu m*5800 mu m with 16000 transistors. Operating video sample rates achieved for the encoder and decoder are 16 MHz and 25 MHz, respectively. The speed results achieved suggest that with a 1- mu m CMOS technology and modest circuit and architectural enhancements, operation of a CMOS VLSI DPCM encoder/decoder should be possible at a 48 MHz HDTV sample rate.<>