Clock skew reduction approach for standard cell

Five clock treatments are evaluated by SPICE simulation. The wide trunk-line with balanced output short sub-buffering scheme is the best way to reduce the clock skew and delay. In order to realize this scheme, a special clock treatment has been developed. This includes insertion of sub-buffers, regeneration of channel relation trees and special global routing. Maximum clock delay and skew are simulated to be 3.6 ns and 1.4 ns respectively under the condition of 2000 fanouts and 15-mm-square die size on 1.0 mu m design rule. This approach will be available on both TC24SC (1.0 mu m) and TC25SC (0.8 mu m) standard cell.<
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