A 7-channel level generator chip for a VLSI digital tester

The automatic test equipment (ATE) level generator chip integrates all the per-pin analog levels required in a VLSI digital tester. This system chip was specified and defined at an architectural level by ATE engineers and implemented using a building block approach by the semicustom supplier working from standard function cells. The chip is integrated on an n-well junction-isolated merged bipolar-CMOS process build on a p wafer with a p epitaxial layer. BiCMOS has self-aligned polysilicon gate PMOS and NMOS devices and n-p-n, lateral, and vertical p-n-p devices. The process includes laser-trimmed thin film resistors and two-layer metal interconnect.<
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