Fast and practical false-path elimination method for large SoC designs

In this paper, we propose a new fast and practical technique to eliminate known false paths during static timing analysis (STA). False paths are verified fast using additional information stored in arrival times, which is a pass-through history of exceptional nodes. The information can be constructed with small memory overhead because an individual false path list is not managed at each arrival time. We adapted this method to classical arrival time computation and a critical path searching algorithm. The feature is used in CubicTime, our full-chip gate level static timing analyzer, supporting multiple clock domains. We describe the details of our algorithm and the experimental results compared to those of our previous method and a de-facto industry-standard STA tool.