Efficient VLSI design of a pulse shaping filter and DAC interface for W-CDMA transmission

This paper presents the design and VLSI implementation of a pulse shaping filter architecture for FDD W-CDMA transmission satisfying 3GPP specifications. We first study a filter design method to find the minimum number of coefficients and bits per coefficients to achieve the 3GPP requirements. Then, we propose a multiplierless linear phase FIR filter architecture implemented with an oversampling factor of four and minimizing size and power consumption. Design and requirements of the postfiltering elements and DAC interface are also defined. The implementation has been tested with an overall baseband transmission chain and results concerning the hardware complexity are given.