Hardware nested looping of parameterized and embedded DSP core

In this paper, a hardware nested looping structure is proposed for a parameterized and embedded DSP core. The zero-overhead looping scheme used does not cause any clock latency during loop execution. An optional buffer memory for the instructions in the loop is used to save power consumption of the memory access during the transaction of the program memory fetch. The size of instruction buffer and nested loop depth are parameterized parameters in our NCU/spl I.bar/DSP core design. Design examples show that there is only a 3% hardware overhead for the nested hardware looping.