The CIP2k first level trigger system at the H1 experiment at HERA

The ep-collider HERA at DESY, Germany, and the high energy physics experiments HI and ZEUS were upgraded in the years 2000-2002. The expected specified luminosity is five times higher than before. One of the upgrade projects was to build a set of new multi wire proportional chambers (CIP2k) providing information to distinguish between events induced by the beam background, and ep-interactions on an early stage of the trigger. This new first level trigger system provides a trigger decision using a total of about 10,000 channels of the chamber at a speed of 10.4 MHz. The system is realized in large field programmable gate arrays (FPGA) in order to comply with the timing requirements, which are necessary for a dead time free trigger decision within 1.5 /spl mu/s. This is achieved by simultaneous event pipelining and readout while preparing the trigger decision. The total data throughput rate is 108 GB/s. The system is developed in the hardware description language Verilog. Special attention is drawn to an integrated error correction system in the FPGA, which cannot be realized in hard wired electronics. This system is necessary to ensure maximum pattern recognition efficiency even at high occupancy. The CIP2k trigger system was installed in 2001 in parallel to the HERA startup and is now being commissioned in order to reach its best performance. The flexible programmable hardware clearly is a big advantage here.