Redundancy analysis simulation for electrical die sorting (EDS) process

It takes about four to five weeks to fabricate a semiconductor memory device. As the fabrication process consists of various operations, there is a possibility of fabricating a final product with defects. It would be impossible for us to repair a memory device if it has numerous defects that cannot be dealt with properly. However, in case of a small number of defects, it is desirable to reuse a defective die (standard unit measuring a device on a wafer) after repair rather than to discard it, because reuse is an essential element for memory device manufactures to cut costs effectively. To perform the reuse, laser-repair process and redundancy analysis for setting an accurate target in the laser-repair process is needed. Cost reduction was attempted by reducing time in carrying out a new type of redundancy analysis after simulating each defect.