A novel equalization technique for 54 Mbps OFDM systems

When the maximum delay spread exceeds the guard interval, a time domain equalization (TEQ) technique for 54 Mbps IEEE 802.11a orthogonal frequency division multiplexing (OFDM) system is proposed in [Naihua Yuan et al., July 2003] to shorten the effective channel impulse response. The proposed algorithm has a reduced computational complexity for practical use. In this paper the detailed design and implementation of the algorithm in field programmable gate array (FPGA) are presented. In solving the linear equation Aw=B for the optimum TEQ coefficients, the matrix A is proved to be Hermitian and positive definite. The regularities between the elements of A are exploited to reduce hardware complexity. The LDL/sup T/ and LU decompositions are combined in hardware design to find the TEQ coefficients in less than 4 /spl mu/s. To compensate the effective channel impulse response, a radix-4 pipeline fast Fourier transform (FFT) is implemented to perform zero forcing equalization. The hardware design information is provided and the simulation results are compared with the theoretical values. The results verify the chips function properly at 54 Mbps.