Physical compact model for threshold voltage in short-channel double-gate devices

Compact physics/process-based model for threshold voltage in double-gate devices is presented. Drain-induced barrier lowering and short-channel-induced barrier lowering models for double-gate and bulk-Si devices are derived. The validity and predictability of the models are demonstrated and confirmed by numerical device simulation results for extremely scaled (L/sub eff/=25 nm) double-gate and bulk-Si devices.