Optimization of sub-50 nm MOSFETs to mitigate drive current degradation due to silicon recess in S/D

The recess of silicon in the source/drain and extension area severely compromises the performance of sub-50 nm MOSFETs. In this paper we investigate the influence of silicon recess on the transistor characteristics using process and device simulation, and systematically map the engineering space for optimization of channel, halo, S/D implants, spacer formations, silicidation and integration schemes to mitigate the silicon surface gouging using response surface modeling.