Predictive comparators with adaptive control

We describe an architecture that adds a linear predictor and adaptive control to a comparator to greatly reduce its delay. The linear predictor feeds an estimated future signal to the comparator to compensate for the comparator's inherent delay. On a cycle-by-cycle basis, an adaptive controller adjusts the comparator's bias current to null residual errors that remain after the prediction. Emphasis is placed on low power consumption, including the development of a linear predictor with no static power consumption. In an experimental 1.5-/spl mu/m VLSI chip implementation, our scheme enabled a 45-fold improvement in the power-delay product of a simple comparator. Our scheme is ideally suited for comparators used in synchronous rectification. It is also broadly useful in applications where an asynchronous comparator is required, such as sensor interfaces, oscilloscope triggers, some types of analog-to-digital converters, and spiking-neuron circuits. The difference equations that govern our adaptive scheme may be represented by a unimodal discrete map. Therefore, near the limits of the scheme's stable regime of operation, we were able to experimentally confirm that there was a period-doubling route to chaos.