Defect-oriented dynamic fault models for embedded-SRAMs

This paper presents the results of resistive fault insertion in the core-cell array and in the address decoder of the Infineon 0.13 /spl mu/m embedded-SRAM family. Resistive opens defects were the primary target of this study because of their growing importance in VDSM technologies. Electrical simulations have been performed to evaluate the effects of resistive opens in terms of functional faults detected and verify the presence of timing-dependent faults. Read disturb, deceptive read disturb and dynamic read disturb faults have been reproduced and accurately characterized. The dependence of the fault detection on memory operating conditions, injected resistance value and clock speed have been investigated and the importance of speed testing for dynamic fault models is emphasized. Finally resistive address decoder open faults (ADOF) have been simulated and the conditions for maximum fault detection are discussed as well as the resulting implications for memory test.