Analysis and simulation of a cache architecture for IP packet classification

The paper presents the analysis and simulation results of a fully associative cache architecture for performing IP classification. We have developed a novel replacement algorithm. For optimal performance on different data traces, the administrator can tune the replacement algorithm using a configurable parameter. We have done a detailed analysis of data traces and IP traffic behavioral patterns on a backbone network. By characterizing different flows and exploiting the inter-packet arrival times of a flow, we have obtained interesting and stable results. We have also proved that, by using an effective cache design and by pipelining the hardware architecture, one can obtain packet processing speeds of 5 million packets per second.