Board level reliability evaluation of RF PA module vias

The reliability of RF PA module substrate vias was evaluated using nine different laminate constructions. Variables in the substrate construction included layer count, trace thickness, via wall thickness, via diameter, via plugging, via capping, core material, and process flow at the supplier. A daisy chain module was designed to simulate a typical over molded RF PA module. The body size was 10/spl times/10 mm, with 2 die, 20 components, and 34 LGA I/O pads. Daisy chain nets were formed through 2 via chains, and 1 SMD component chain. Via reliability was measured by temperature cycling at -55/spl deg/C <=> 125/spl deg/C, 2 cph, after pre-conditioning at Jedec L3/240/spl deg/C and L3/260/spl deg/C. Both package level and board level testing was conducted. In the package level tests, it was found that nearly all of the constructions passed the typical qualification requirement of 1000 temperature cycles. However, one construction had failures starting at 600 cycles due to cracks in the knee region of the substrate vias. This construction used a less robust manufacturing flow at the substrate supplier. Three of the nine constructions were evaluated in the board level tests. All three legs passed the 1000 temperature cycle requirement, with the first via failure observed at 1372 cycles. No 2nd level solder joint failures were observed before the test was terminated at 3779 cycles. This robust board level temperature cycling performance is due to large NSMD pads (0.8 mm/spl times/0.8 mm), and small die (1.0 mm/spl times/1.0 mm). Failure analysis was conducted on all test legs to understand crack initiation sites and crack growth paths in the substrate vias.