Optimizing dynamic-threshold DTMOS device performance in an SOI embedded DRAM technology

This paper describes the DC and high frequency characteristics of a dynamic threshold DTMOS n-channel device, fabricated within a low-cost CMOS SOC process which also includes high-density embedded DRAM. The DTMOS device design in this process was previously found to be superior to both grounded body (GB) and floating body (FB) MOSFETs. This DTMOS device achieves kink-free behavior, with gm=936 /spl mu/S//spl mu/m, g/sub out/=36 /spl mu/S//spl mu/m, Ion/Ioff=210 /spl mu/A/0.1 pA, S=67 mV/dec, and fmax=32 GHz at V/sub DD/=1 V. These DTMOS devices are excellent for sub-volt embedded baseband circuits with sufficient performance for RF front-end circuits, thus enabling the combination of embedded DRAM, digital, analog, and RF circuit cores in, ultra-low-power, low-cost SOCs.