Cost-effective approach in LDMOS with partial 0.35/spl mu/m design into conventional 0.6/spl mu/m process

We propose a practical solution, which can provide the same high performance LDMOS as that of the more advanced CMOS design rule with retaining still the low cost of the old technology. More specifically, we have introduced a limited number of 0.35/spl mu/m equivalent mask alignment steps into 0.6/spl mu/m based BCD processes. We have successfully developed 0.6/spl mu/m design based 40V and 50V LDMOS, whose on-resistances are superior to those of 0.35/spl mu/m based LDMOS. The on-resistance of the developed 40V and 50V LDMOS are 54.3 and 69.7 m/spl Omega/ mm/sup 2/, respectively. These values are superior to the reported values of the 0.35/spl mu/m design LDMOS.