Hydrogenated amorphous silicon thin-film transistor arrays fabricated by digital lithography

A jet-printed digital-lithographic method, in place of conventional photolithography, was used to fabricate 64 × 64 pixel (300 μm pitch) matrix addressing thin-film transistor (TFT) arrays. The average hydrogenated amorphous silicon TFT device within an array had a threshold voltage of /spl sim/3.5 V, carrier mobility of 0.7 cm
²
/V/spl middot/s, subthreshold slope of 0.76 V/decade, and an on/off ratio of 10/sup 8/.