A viable self-aligned bottom-gate MOS transistor technology for deep submicron 3-D SRAM

In this paper, the effect of the nonself-aligned process on the performance variation of a bottom-gate metal oxide semiconductor (MOS) transistor is discussed using a device simulator. The simulation results predict that the nonself-aligned bottom-gate MOS transistor cannot be scaled into the deep submicron regions. A simple fully self-aligned bottom-gate (FSABG) metal oxide semiconductor field effect transistor (MOSFET) technology is then proposed and developed. A new technique for forming thermal oxide on poly-Si serving as the bottom-gate dielectric is also investigated. It is found that the quality of the oxide on the poly-Si recrystallized by the metal induced uni-lateral crystallization (MIUC) is much higher than that by the solid phase crystallization (SPC). Deep submicron fully self-aligned bottom-gate pMOS transistors are fabricated successfully using the proposed technology. The experimentally measured results indicate the device performances depend strongly on the channel-width, and get comparable to that of a single crystal MOSFET if the channel width is less than 0.5/spl mu/m. The effects of the channel width on the device performances are discussed. In addition, the experimental results also confirm that the proposed technology has a good control of the channel film thickness.