Ultra-low power and high speed SRAM for mobile applications using single Poly-Si gate 90 nm CMOS technology

High speed and ultra-low power SRAM using single gate CMOS technology was developed. The drive currents of NMOSFET and PMOSFET were 410 /spl mu/A//spl mu/m and 205 /spl mu/A//spl mu/m, respectively. The random access time of 17 ns at 1.65 V operation voltage was achieved for the first time in low power application by the reduction of loading capacitance. Standby current was less than 15 /spl mu/A/chip. The highly manufacturable compact cell of 0.84 /spl mu/m/sup 2/ area was integrated using PR (photo resist) flow technology and novel contact layout.