A single-chip transceiver for 802.11a and Hiperlan2 wireless LANs

A fully integrated transceiver for 802.11a and Hiperlan2 wireless local area network applications is described. This single-chip transceiver employs direct conversion with on-chip channel-select filters and DC offset cancellation servo circuitry, as well as correction loops for maintaining accurate I/Q balancing and transmitter power control. The transceiver exceeds both WLAN standard requirements for the 54 Mbps mode, demonstrating a receiver sensitivity of -75 dBm for this mode. A highly flexible interface allows a variety of baseband processors to interface with this chip.