Enhancement-mode power heterojunction FET utilizing re-grown p/sup +/-GaAs gate with negligible off-state leakage current

An enhancement-mode power heterojunction FET utilizing a re-grown p/sup +/-GaAs gate (p/sup +/-gate HJFET) was developed for cellular applications. The p/sup +/-gate HJFET exhibited a high maximum drain current of 400 mA/mm and a gate forward turn-on voltage of 1.15 V with threshold voltage (V/sub T/) of +0.5 V. A small V/sub T/ standard deviation of 20 mV was obtained. The 32 mm gate width device has an extremely low off-state leakage current of 0.02 /spl mu/A at drain-to-source voltage (V/sub ds/) of 3.0 V and gate-to-source voltage of 0.0 V and at RT. Under single 3.2 V operation, the 32 mm device delivered 35 dBm output power, 11.9 dB associated gain and 73% power added efficiency at 950 MHz. Even operated at V/sub ds/ of 1.0 V, the device exhibited a high PAE of 70%. The developed p/sup +/-gate HJFET is promising for no drain bias switches and single voltage operation power amplifiers.