Algorithmic partial analog-to-digital conversion in mixed-signal array processors

We present an algorithmic analog-to-digital converter (ADC) architecture for large-scale parallel quantization of internally analog variables in externally digital array processors. The converter quantizes and accumulates a binary weighted sequence of partial binary-binary matrix-vector products computed on the analog array, under presentation of bit-serial inputs in descending binary order. The architecture combines algorithmic conversion of the residue, as in a standard algorithmic ADC, with synchronous accumulation of the partial products from the array. In conjunction with row-parallel digital storage of matrix elements in the array, two pipelined architectures are presented to accumulate partial products with common binary weight across rows: row-parallel ADC with digital post-accumulation, and row-cumulative ADC with analog pre-accumulation. Simulation results are presented to quantify the trade-off in precision and area for full-parallel flash, and row-parallel and row-cumulative partial algorithmic, analog-to-digital conversion on the array.