Negative substrate bias enhanced breakdown hardness in ultra-thin oxide pMOSFETs

Negative substrate bias enhanced breakdown hardness in ultra-thin oxide (1.4 nm) pMOS is observed. This result is believed to be due to the increase of hole stress current during breakdown progression via breakdown induced carrier heating. Numerical analysis of the substrate bias effect on hole tunneling current is performed to support the proposed theory. This phenomenon is particularly significant to gate oxide reliability in floating substrate (PD-SOI) or forward-biased substrate devices.