On the degradation of p-MOSFETs in analog and RF circuits under inhomogeneous negative bias temperature stress

The effect of inhomogeneous Negative Bias Temperature Stress (NBTS) applied to p-MOS transistors under analog and RF CMOS operating conditions is investigated. Experimental data of a 0.18 /spl mu/m standard CMOS process are presented and an analytical model is derived to physically explain the effect of stress on the device characteristics. The impact of inhomogeneous NBTS on device lifetime is considered and compared to the homogeneous case.