Polysilicon resistive heated scribe lane test structure for productive wafer level reliability monitoring of NBTI

A polysilicon resistive heated test structure was designed with a MOSFET embedded between two polysilicon heater stripes. A 4-terminal metal resistor above the heaters allows temperature control via the temperature coefficient of the resistance. A stress algorithm performs simultaneous thermal and electrical stress. The real device temperature is gained by a comparison of the temperature measured at the metal level and the pn-junction temperature measured by the forward diode characteristics. Bias Temperature Instability stress results from this structure are presented.