Test time reduction methods for yield test structures

Complexity of integrated circuits has led to hundreds of millions of transistors, wiring lines, and layer to layer via connections on every chip. To allow accurate yield evaluation, it is required that process characterization test chips grow in complexity as well which has let to a significant bottleneck in testing them. Wafers that could be tested in less than two hours in a 0.35/spl mu/m technology now require 10 hours and more in a 0.13/spl mu/m technology. This paper will present methods how test structures can be redesigned to better support testing. Based on those we will present modified test algorithms that will significantly reduce the test time by 50% and more, which will accelerate data analysis and increases efficient use of parametric test systems.