Dual damascene trench depth control by Irm/spl trade/: a novel interferometric endpoint system

Etching dielectric trenches on the wafer for copper interconnect without using a middle etch stop layer is becoming part of mainstream wafer fabrication processes, mainly due to significant lower manufacturing cost and lower effective k-value of the dielectric film stack. In this paper, we present a novel in-situ interferometric technique to control the trench depth for various types of patterned dielectric films, including silicon oxide, FSG (fluorinated silicon glass), low-k CVD Black Diamond/spl trade/, and low k spin-on materials. This paper presents data on etching various dielectric structure trench wafers for both CVD and spin-on low-k materials in Applied Materials MERIE etch reactors. A good correlation between predicted etch depth using interferometric signals and SEM depth data is obtained.