Fast wafer level monitoring of stress induced leakage current in deep sub-micron embedded non-volatile memory processes

A new fast wafer level SILC monitoring method, based on parallel floating gate cells, is reported here. The measurement is straightforward, and the stress measurement is not time consuming. It consists of bi-directional FN tunneling stress (to degrade the tunnel oxide) and a negative voltage gate stress (to reveal the SILC). An empirical SILC parameter has been defined as the lowest cell V/sub t/ in the parallel NVM array. This method has been implemented as part of end-of-line measurements in Philips embedded flash processes, and has been proven to be very effective and powerful in experimental split analysis, process reliability monitoring/control, and process transfers.