A 1 V, 1.9 GHz folded dual-gate mixer in CMOS

This paper describes a low-power folded dual-gate mixer implemented in a standard 0.25 /spl mu/m CMOS process. The mixer exhibits 3.6 dB gain, -1 dBm IIP3, 12.5 dB noise figure operating at 1.9 GHz from a 1 V supply and with power dissipation of 4.5 mW.