Empirical performance prediction for IFFT/FFT cores for OFDM systems-on-a-chip

Quick and accurate prediction of area, speed, and power of IP cores for SoC implementations reduces the design time and thus the overall cost. Accurate performance estimation early in the design cycle also is valuable for identifying trade-offs in the different blocks that make up an SoC. This work provides an empirical estimation method for IFFT/FFT blocks in multicarrier (OFDM, DMT) systems. The relative accuracy of the predictions allows the comparison of implementation alternatives, and the absolute accuracy enables the prediction of the final performance of fabricated cores. The methodology was verified through the fabrication of a 0.18 /spl mu/m CMOS test chip. The methodology inefficiency factor (MIF) is introduced as metric for evaluating the area efficiency of a digital design flow.