A low power 10 bit 80 MSPS pipelined ADC in digital CMOS process

This paper describes a 10 bit 80 MSPS low power ADC designed in a 0.18 /spl mu/m digital CMOS process for an 802.11a baseband PHY chip. The receive channel in the AFE consists of dual ADCs used to digitize the I & Q channels in a direct conversion receiver. Novel features in this design include a 6-bit offset cancellation DAC integrated in the S/H and a amplifier sharing topology that help in reducing overall power and area. Low power is achieved through the use of the digital supply (1.8 V) provided to the chip which allows the fastest digital core transistors to be used in the design without reliability issues and also makes the design suitable for integration with the digital baseband section. Each ADC consumes less than 60 mW of analog power including the reference and about 20 mW of switching power. The device is designed for -62 dB THD performance and 58 dB SNR for an 11 MHz signal band making it among the lowest power ADCs in its class described in literature.