Substrate coupling fault testing in system-on-a-chip digital circuits

Modern System-on-a-Chip (SoC) systems are implemented using deep submicron technologies and operate at the GHz range. Logic faults caused by substrate coupling becomes a significant concern. Robust SoC designs must be able to predict and test substrate-coupling hazards in the fabricated circuits. In this paper, we devise an efficient testing strategy that identifies excessive substrate coupling. Faults are located based on drive strength and the coupling response from the substrate model.