A CMOS phase/frequency detector with a high-speed low-power D-type master-slave flip-flop

An improved CMOS Phase/Frequency Detector (PFD) is presented. A high-speed low-power CMOS D-type master-slave flip-flop is proposed and adopted in the PFD. Higher speed and lower power operation are attributed to the reduced node capacitance. Charge-sharing phenomena are circumvented in the proposed PFD. The proposed PFD shows improvement in frequency sensitivity at high operating frequency. The proposed PFD is suitable for high-speed low-power operation.