SOI implementation of novel triangular layout structures for microwave power transistor applications

A novel layout scheme for MOS microwave power transistors based on a triangular unit cell was implemented in silicon on insulator (SOI) technology. The triangular cell layout significantly reduces gate resistance, R/sub g/, and source resistance R/sub s/, when compared to multi-finger large transistors of equivalent size, leading to large gains in current gain bandwidth product, f/sub t/, and unity power gain bandwidth, f/sub max/. Large PMOS and NMOS devices varying from 435 micron to 2237 micron channel width were implemented using Peregrine's half micron UTSi/spl reg/ process. On-wafer S-parameter test data was acquired and equivalent circuits were derived. Data analysis was hampered by unexplained spurious resonances which are currently under investigation, otherwise measured frequency characteristics of the test transistors are near the limits imposed by the process.