MAP decoder architecture: soft IP for SOC applications

A soft IP for MAP decoder is presented. The Soft IP supports different design objectives, such as high performance and area efficiency. System parameters and required performance configure the IP yielding the architecture. The IP is realized using VHDL and scripts that accept design specification from the designer and automatically generate a synthesizable HDL. FPGA platform is used for rapidly prototyping the IP core. Prototyping adhering the third generation standard yields architectures range from 56 Kbps up to 20 Mbps.